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7. CISC vs RISC

CISC stands for Complex Insruction Set Computers and RISC stands for Reduced Instruction Set Computer and they represent two lines of thought when designing a new computer chip.

Question: Is it better to make more complicated instructions available that take many cycles to complete or is it better to restrict you to a smaller, simpler instruction set that each only take a single cycle to complete?

Answer: It depends.

And this is the question behind whether CISC or RISC is the better approach.

Up until recently, the major chip makers preferred the CISC approach. Each generation of their chips offered larger and richer instruction sets compared to the one before. But now the RISC approach seems to be favoured one.

Say you want to multiply two numbers 'a' and 'b'.

In a CISC chip a single instruction such as MULT a,b is available. The chip-maker adds more and more complex hardware circuits within the CPU to carry out these instructions. So the trade-off is more complex hardware to support simpler software coding.

The compiler, when seeing a multiply command written in high level language source code can generate a single machine code instruction to carry out the task - job done.

In a RISC chip it is the other way around - keep the hardware simple and let the software be more complicated. There may be no single multiply instruction available, so the compiler now has to generate more lines of code such as

LOAD a from memory into register1

LOAD b from memory into a register2

PROD Register1, Register2 (multiply)

STORE Answer back into memory

But each of those instructions can be carried out in a single cycle. You can also use the pipeline method to speed it up even more (since 'a' and 'b' do not depend on each other). So overall the RISC approach may be faster.

Challenge see if you can find out one extra fact on this topic that we haven't already told you

Click on this link: RISC - CISC debate

Comparison

CISC RISC
Has more complex hardware Has simpler hardware
More compact software code More complicated software code
Takes more cycles per instruction Takes one cycle per instruction
Can use less RAM as no need to store intermediate results Can use more RAM to handle intermediate results
 

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