Short for Reduced Instruction Set Computing.
The diagram below shows the RISC approach taken to processor design.
RISC is an alternative approach to CISC. With RISC, the idea is to have a small instruction set for the CPU so only the most frequently used instructions are available. By reducing the instruction set, the CPU can access and process the instruction faster.
The RISC approach to processor design means fewer transistors are needed to handle the smaller CPU instruction set. Thus RISC CPUs tend to be smaller in physical size than CISC CPUs.
Also, fewer transistors means a lower power consumption, less heat and lower cost.
So rather than using many transistors to handle large, complex instructions, RISC CPUs have many registers to hold a lot of smaller, simpler instructions.
Each of these smaller instructions can be carried out in a single clock cycle (ideally), which means it is much simpler to use pipelining to improve performance.
Because there are fewer instructions available, the compiler now has to generate more lines of machine code to do the same task that could have been done with one instruction by using a CISC CPU. Also, a RISC system will need more memory to store the additional instructions that are created.
The RISC compromise is simpler, lower power hardware but more memory and more code for a given program.
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Click on this link: Advantages of RISC cpu